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19-3712; Rev 0; 5/05
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
General Description
The MAX1332/MAX1333 2-channel, serial-output, 12-bit, analog-to-digital converters (ADCs) feature two true-differential analog inputs and offer outstanding noise immunity and dynamic performance. Both devices easily interface with SPITM/QSPITM/MICROWIRETM and standard digital signal processors (DSPs). The MAX1332 operates from a single supply of +4.75V to +5.25V with sampling rates up to 3Msps. The MAX1333 operates from a single supply of +2.7V to +3.6V with sampling rates up to 2Msps. These devices feature a partial power-down mode and a full powerdown mode that reduce the supply current to 3.3mA and 0.2A, respectively. Also featured is a separate power supply input (DVDD) that allows direct interfacing to +2.7V to +3.6V digital logic. The fast conversion speed, low power dissipation, excellent AC performance, and DC accuracy (0.6 LSB INL) make the MAX1332/MAX1333 ideal for industrial process control, motor control, and base-station applications. The MAX1332/MAX1333 are available in a space-saving (3mm x 3mm), 16-pin, TQFN package and operate over the extended (-40C to +85C) temperature range.
Features
3Msps Sampling Rate (+5V, MAX1332) 2Msps Sampling Rate (+3V, MAX1333) Separate Logic Supply: +2.7V to +3.6V Two True-Differential Analog Input Channels Bipolar/Unipolar Selection Input Only 38mW (typ) Power Consumption Only 2A (max) Shutdown Current High-Speed, SPI-Compatible, 3-Wire Serial Interface 2MHz Full-Linear Bandwidth 71.4dB SINAD and -93dB THD at 525kHz Input Frequency No Pipeline Delays Space-Saving (3mm x 3mm), 16-Pin, TQFN Package
MAX1332/MAX1333
Ordering Information
PART MAX1333ETE TEMP RANGE PIN-PACKAGE -40C to +85C 16 TQFN-EP** (3mm x 3mm) MAX1332ETE* -40C to +85C 16 TQFN-EP** (3mm x 3mm)
Applications
Data Acquisition Bill Validation Motor Control Base Stations High-Speed Modems Optical Sensors Industrial Process Control
*Future product--contact factory for availability. **EP = Exposed paddle. Selector Guide and Pin Configuration appear at end of data sheet.
Typical Operating Circuit
+2.7V TO +3.6V +4.75V TO +5.25V 1F 0.1F AVDD + DIFFERENTIAL INPUTS + REF INPUT VOLTAGE 0.1F AGND AIN1P AIN1N AIN0P AIN0N REF 1F MAX1332 CHSEL CNVST SCLK DOUT AGND DGND C/DSP DVDD SHDN BIP/UNI 0.1F 1F
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND (MAX1332) ......................................-0.3V to +6V AVDD to AGND (MAX1333) ......................................-0.3V to +4V DVDD to DGND.........................................................-0.3V to +4V AGND to DGND.....................................................-0.3V to +0.3V SCLK, CNVST, SHDN, CHSEL, BIP/UNI, DOUT to DGND ...................................-0.3V to (DVDD + 0.3V) AIN0P, AIN0N, AIN1P, AIN1N, REF to AGND...................................................-0.3V to (AVDD + 0.3V) Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin TQFN (derate 17.5mW/C above +70C) ....1398.6mW Operating Temperature Range MAX133_ETE ...................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (MAX1332)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +3.6V, fSCLK = 48MHz, VREF = 4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Offset-Error Temperature Coefficient Gain-Error Temperature Coefficient Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Isolation Full-Linear Bandwidth Full-Power Bandwidth Small-Signal Bandwidth CONVERSION RATE Minimum Conversion Time Maximum Throughput Rate Minimum Track-and-Hold Acquisition Time tACQ Figure 5 tCONV Figure 5 3 52 271 ns Msps ns SINAD > 68dB SNR SINAD THD SFDR 84 70 70 SYMBOL N INL DNL CONDITIONS MIN 12 0.6 0.6 0.9 0.6 0.2 1.1 1.0 1.0 3.0 6.0 TYP MAX UNITS Bits LSB LSB LSB LSB ppm/C ppm/C
DC ACCURACY (BIP/UNI = DGND) (Note 1)
DYNAMIC SPECIFICATIONS (AIN = -0.2dBFS, fIN = 525kHz, BIP/UNI = DVDD, unless otherwise noted) (Note 1) 71.5 71.4 -93 93 76 2 6 6 -84 dB dB dBc dBc dB MHz MHz MHz
2
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX1332) (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +3.6V, fSCLK = 48MHz, VREF = 4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Aperture Delay Aperture Jitter Differential Input Voltage Range (VAIN_P - VAIN_N) Absolute Input Voltage Range DC Leakage Current Input Capacitance REFERENCE INPUT (REF) REF Input Voltage Range REF Input Capacitance REF DC Leakage Current ILKG CIN 14 AVDD + 50mV 14 10 0.3 x DVDD 0.7 x DVDD 100 IILKG CIN VOL VOH ILKGT COUT AVDD DVDD Normal mode; average current (fSAMPLE = 3MHz, fSCLK = 48MHz) Partial power-down mode Full power-down mode ISINK = 5mA ISOURCE = 1mA Between conversions, CNVST = DVDD Between conversions, CNVST = DVDD 4.75 2.7 11 3.5 0.1 15 5.25 3.6 12 6 2 A DVDD 0.5 1 0.2 15 0.4 5 SYMBOL tAD tAJ Figure 21 Figure 21 BIP/UNI = DGND BIP/UNI = DVDD 0 -VREF / 2 AGND - 50mV CONDITIONS MIN TYP <10 <10 VREF +VREF / 2 AVDD + 50mV 1 V A pF MAX UNITS ns ps V
MAX1332/MAX1333
DIFFERENTIAL ANALOG INPUTS (AIN0P, AIN0N, AIN1P, AIN1N) VIN
VREF CREF IREF
1.0
V pF A
DIGITAL INPUTS (SCLK, CNVST, SHDN, CHSEL, BIP/UNI) Input-Voltage Low Input-Voltage High Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (DOUT) Output-Voltage Low Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage V V mA V V A pF VIL VIH V V mV A pF
Analog Supply Current
IAVDD
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3
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
ELECTRICAL CHARACTERISTICS (MAX1332) (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +3.6V, fSCLK = 48MHz, VREF = 4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS Average current (fSAMPLE = 3MHz, fSCLK = 48MHz, zero-scale input) Digital Supply Current IDVDD Power-down (fSCLK = 48MHz), CNVST = DVDD Static; all digital inputs are connected to DVDD or DGND Power-Supply Rejection PSR AVDD = 4.75V to 5.25V, full-scale input MIN TYP 4.5 15 0.2 MAX 7 30 A 2 2 mV UNITS mA
TIMING CHARACTERISTICS (MAX1332) (Figure 4)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SCLK Clock Period SCLK Pulse Width CNVST Rise to DOUT Disable CNVST Fall to DOUT Enable CHSEL to CNVST Fall Setup BIP/UNI to CNVST Fall Setup CNVST Fall to CHSEL Hold SCLK Fall to BIP/UNI Hold DOUT Remains Valid After SCLK SCLK Rise to DOUT Transition CNVST to SCLK Rise SCLK Rise to CNVST CNVST Pulse Width Minimum Recovery Time (Full Power-Down) Minimum Recovery Time (Partial Power-Down) SYMBOL tCP tSPW tCRDD tCFDE tCHCF tBUCF tCFCH tCFBU tDHOLD tDOT tSETUP tHOLD tCSW tFPD tPPD From CNVST fall or SHDN rise From CNVST fall CLOAD = 0pF (Note 2) CLOAD = 30pF 6 0 6 4 500 CONDITIONS MIN 20.8 6 15 15 40 40 0 0 1 2 6 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns s ns
Note 1: Tested with AVDD = 4.75V and DVDD = +2.7V. Note 2: Guaranteed by design, not production tested.
4
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX1333)
(AVDD = +2.7V to +3.6V, DVDD = +2.7V to AVDD, fSCLK = 32MHz, VREF = 2.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Offset-Error Temperature Coefficient Gain-Error Temperature Coefficient Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Isolation Full-Linear Bandwidth Full-Power Bandwidth Small-Signal Bandwidth CONVERSION RATE Minimum Conversion Time Maximum Throughput Rate Minimum Track-and-Hold Acquisition Time Aperture Delay Aperture Jitter Differential Input Voltage Range (VAIN_P - VAIN_N) Absolute Input Voltage Range DC Leakage Current ILKG tACQ tAD tAJ Figure 5 Figure 21 Figure 21 BIP/UNI = DGND BIP/ UNI = DVDD 0 -VREF / 2 AGND - 50mV <10 <10 VREF +VREF / 2 AVDD + 50mV 1 tCONV Figure 5 2.0 78 406 ns Msps ns ns ps SINAD > 68dB SNR SINAD THD SFDR 83.5 70 70 SYMBOL N INL DNL CONDITIONS MIN 12 0.6 0.6 0.9 0.6 1.1 0.2 1.0 1.0 3.0 6.0 TYP MAX UNITS Bits LSB LSB LSB LSB ppm/C ppm/C DC ACCURACY (Note 3) (BIP/UNI = DGND)
MAX1332/MAX1333
DYNAMIC SPECIFICATIONS (AIN = -0.2dBFS, fIN = 525kHz, BIP/UNI = DVDD, unless otherwise noted) (Note 3) 71.5 71.4 -93 93 76 1.7 5.5 5 -86.5 dB dB dBc dBc dB MHz MHz MHz
DIFFERENTIAL ANALOG INPUTS (AIN0P, AIN0N, AIN1P, AIN1N) VIN V
V A
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5
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
ELECTRICAL CHARACTERISTICS (MAX1333) (continued)
(AVDD = +2.7V to +3.6V, DVDD = +2.7V to AVDD, fSCLK = 32MHz, VREF = 2.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Input Capacitance REFERENCE INPUT (REF) REF Input Voltage REF Input Capacitance REF DC Leakage Current SYMBOL CIN CONDITIONS MIN TYP 14 AVDD + 50mV 14 10 0.3 x DVDD 0.7 x DVDD 100 IILKG CIN VOL VOH ILKGT COUT AVDD DVDD Normal mode; average current (fSAMPLE = 2MHz, fSCLK = 32MHz) Partial power-down mode Full power-down mode Average current (fSAMPLE = 2MHz, fSCLK = 32MHz, zero-scale input) Digital Supply Current IDVDD Power-down (fSCLK = 32MHz, CNVST = DVDD) Static; all digital inputs are connected to DVDD or DGND Positive Supply Rejection PSR AVDD = 2.7V to 3.6V, full-scale input ISINK = 5mA ISOURCE = 1mA Between conversions, CNVST = DVDD Between conversions, CNVST = DVDD 2.7 2.7 9.5 3.3 0.1 3 10 0.2 15 3.6 AVDD 11.5 4 2 5.4 20 A 2 3 mV A mA DVDD 0.5 1 0.2 15 0.4 5 MAX UNITS pF
VREF CREF IREF
1.0
V pF A
DIGITAL INPUTS (SCLK, CNVST, SHDN, CHSEL, BIP/UNI) Input-Voltage Low Input-Voltage High Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (DOUT) Output-Voltage Low Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage V V mA V V A pF VIL VIH V V mV A pF
Analog Supply Current
IAVDD
6
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
TIMING CHARACTERISTICS (MAX1333) (Figure 4)
(AVDD = +2.7V to +3.6V, DVDD = +2.7V to AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SCLK Clock Period SCLK Pulse Width CNVST Rise to DOUT Disable CNVST Fall to DOUT Enable CHSEL to CNVST Fall Setup BIP/UNI to CNVST Fall Setup CNVST Fall to CHSEL Hold SCLK Fall to BIP/UNI Hold DOUT Remains Valid After SCLK SCLK Rise to DOUT Transition CNVST to SCLK Rise SCLK Rise to CNVST CNVST Pulse Width Minimum Recovery Time (Full Power-Down) Minimum Recovery Time (Partial Power-Down) SYMBOL tCP tCPW tCRDD tCFDE tCHCF tBUCF tCFCH tCFBU tDHOLD tDOT tSETUP tHOLD tCSW tFPD tPPD From CNVST fall or SHDN rise From CNVST fall CLOAD = 0pF (Note 4) CLOAD = 30pF 6 0 6 4 500 CONDITIONS MIN 31.2 10 15 15 50 50 0 0 1 2 6 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns s ns
MAX1332/MAX1333
Note 3: Tested with AVDD = DVDD = +2.7V. Note 4: Guaranteed by design, not production tested.
DVDD
6k
DOUT DOUT
6k
30pF DGND
30pF DGND b) HIGH IMPEDANCE TO VOL, VOH TO VOL, AND VOL TO HIGH IMPEDANCE
a) HIGH IMPEDANCE TO VOH, VOL TO VOH, AND VOH TO HIGH IMPEDANCE
Figure 1. Load Circuits for Enable/Disable Times
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7
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
Typical Operating Characteristics
(AVDD = +5V, DVDD = +3V, VREF = 4.096V, fSCLK = 64MHz. TA = +25C, unless otherwise noted.)
MAX1332
OFFSET ERROR vs. AVDD
MAX1332 toc01
GAIN ERROR vs. AVDD
1.5 1.0 GAIN ERROR (LSB) 0.5 0 -0.5 -1.0
MAX1332 toc02
2.0 1.5 OFFSET ERROR (LSB) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 4.75 4.85 4.95 5.05 5.15 DVDD = +3V fSCLK = 64MHz
2.0
-1.5 -2.0 5.25 4.75 4.85 4.95
DVDD = +3V fSCLK = 64MHz 5.05 5.15 5.25
AVDD (V)
AVDD (V)
GAIN ERROR vs. AVDD
MAX1332 toc03
AVDD SUPPLY CURRENT vs. TEMPERATURE
11.8 11.6 11.4 IAVDD (mA) 11.2 11.0 10.8 10.6
MAX1332 toc04
2.0 1.5 1.0 GAIN ERROR (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 4.75 4.85 4.95 5.05 5.15 DVDD = +3V fSCLK = 64MHz
12.0
10.4 10.2 10.0 5.25 -40 -15
ZERO-SCALE INPUT fSCLK = 64MHz 10 35 60 85
AVDD (V)
TEMPERATURE (C)
AVDD SUPPLY CURRENT vs. fSCLK
MAX1332 toc05
AVDD SUPPLY CURRENT vs. AVDD
12.5 12.0 11.5 IAVDD (mA) 11.0 10.5 10.0 9.5 9.0 8.5 8.0 DVDD = +3V ZERO-SCALE INPUT fSCLK = 64MHz 4.75 4.85 4.95 5.05 5.15 5.25
MAX1332 toc06
12.0 11.5 11.0 IAVDD (mA) 10.5 10.0 9.5 9.0 8.5 8.0 0 8 16 24 32 40 48 56
13.0
64
fSCLK (MHz)
AVDD (V)
8
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = +3V, VREF = 4.096V, fSCLK = 64MHz. TA = +25C, unless otherwise noted.)
MAX1332/MAX1333
MAX1332
DVDD SUPPLY CURRENT vs. TEMPERATURE
MAX1332 toc07
DVDD SUPPLY CURRENT vs. fSCLK
MAX1332 toc08
DVDD SUPPLY CURRENT vs. DVDD
MAX1332 toc09
6.0 5.5 5.0 IDVDD (mA)
6 5 4 IDVDD (mA) 3 2
8 7 6 IDVDD (mA) 5 4 3 2 AVDD = +5V ZERO-SCALE INPUT fSCLK = 64MHz
4.5 4.0 3.5 3.0 2.5 2.0 -40 -15 10 35 60 85 TEMPERATURE (C) ZERO-SCALE INPUT fSCLK = 64MHz
1 0 0 8 16 24 32 40 48 56 64 fSCLK (MHz)
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 DVDD (V)
TOTAL SUPPLY CURRENT vs. THROUGHPUT RATE
NO POWER-DOWN IAVDD + IDVDD (mA)
MAX1332 toc10
100
10
FULL POWER-DOWN
PARTIAL POWER-DOWN 1
0.1 0.001
0.01
0.1 fCNVST (MHz)
1
10
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9
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
Typical Operating Characteristics (continued)
(AVDD = +3V, DVDD = +3V, VREF = 2.5V, fSCLK = 40MHz. TA = +25C, unless otherwise noted.)
MAX1333
INTEGRAL NONLINEARITY vs. OUTPUT CODE
MAX1333 toc01
DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE
MAX1333 toc02
OFFSET ERROR vs. TEMPERATURE
1.5 OFFSET ERROR (LSB) 1.0 0.5 0 -0.5 -1.0 -1.5 AVDD = +3V -2.0
MAX1333 toc03
1.0 0.8 0.6 0.4 fSCLK = 32MHz
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 fSCLK = 32MHz
2.0
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (C)
OFFSET ERROR vs. AVDD
MAX1333 toc04
GAIN ERROR vs. TEMPERATURE
MAX1333 toc05
GAIN ERROR vs. AVDD
1.5 1.0 GAIN ERROR (LSB) 0.5 0 -0.5 -1.0 -1.5 DVDD = AVDD
MAX1333 toc06
4 3 OFFSET ERROR (LSB) 2 1 0 -1 -2 -3 -4 DVDD = AVDD
2.0 1.5 1.0 GAIN ERROR (LSB) 0.5 0 -0.5 -1.0 -1.5 AVDD = +3V -2.0
2.0
-2.0 -40 -15 10 35 60 85 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD (V) TEMPERATURE (C)
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD (V)
AVDD SUPPLY CURRENT vs. TEMPERATURE
MAX1333 toc07
AVDD SUPPLY CURRENT vs. fSCLK
MAX1333 toc08
AVDD SUPPLY CURRENT vs. AVDD
11.5 11.0 IAVDD (mA) 10.5 10.0 9.5 9.0 8.5 8.0 AVDD = DVDD ZERO-SCALE INPUT fSCLK = 40MHz 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD (V)
MAX1333 toc09
12.0 11.5 11.0 IAVDD (mA)
12.0 11.5 11.0 IAVDD (mA) 10.5 10.0 9.5 9.0
12.0
10.5 10.0 9.5 9.0 8.5 8.0 -40 -15 10 35 60 85 TEMPERATURE (C) ZERO-SCALE INPUT fSCLK = 40MHz
8.5 8.0 0 5 10 15 20 25 30 35 40 fSCLK (MHz)
10
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
Typical Operating Characteristics (continued)
(AVDD = +3V, DVDD = +3V, VREF = 2.5V, fSCLK = 40MHz. TA = +25C, unless otherwise noted.)
MAX1332/MAX1333
MAX1333
DVDD SUPPLY CURRENT vs. TEMPERATURE
MAX1333 toc10
DVDD SUPPLY CURRENT vs. fSCLK
MAX1333 toc11
DVDD SUPPLY CURRENT vs. DVDD
3.5 3.0 IDVDD (mA) 2.5 2.0 1.5 1.0 0.5 0 AVDD = +3V ZERO-SCALE INPUT fSCLK = 40MHz 2.70 2.75 2.80 2.85 DVDD (V) 2.90 2.95 3.00
MAX1333 toc12
4.00 3.75 3.50 3.25 3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 -40 -15 10 IDVDD (mA)
4.0 3.5 3.0 IDVDD (mA) 2.5 2.0 1.5 1.0
4.0
ZERO-SCALE INPUT fSCLK = 40MHz 35 60 85
0.5 0 0 5 10 15 20 25 30 35 40
TEMPERATURE (C)
fSCLK (MHz)
SINAD vs. INPUT FREQUENCY
MAX1333 toc13
SFDR vs. INPUT FREQUENCY
MAX1333 toc14
THD vs. INPUT FREQUENCY
MAX1333 toc15
72
100
-70
70
94
-76
SFDR (dBc)
SINAD (dB)
68
88
THD (dBc)
-82
66
82
-88
64 fSCLK = 32MHz 62 0 400 800 1200 1600 2000 INPUT FREQUENCY (kHz)
76 fSCLK = 32MHz 70 0 400 800 1200 1600 2000 INPUT FREQUENCY (kHz)
-94 fSCLK = 32MHz -100 0 400 800 1200 1600 2000 INPUT FREQUENCY (kHz)
OUTPUT AMPLITUDE vs. INPUT FREQUENCY
MAX1333 toc16
TOTAL SUPPLY CURRENT vs. THROUGHPUT RATE
NO POWER-DOWN IAVDD + IDVDD (mA)
MAX1333 toc17
0 -1 OUTPUT AMPLITUDE (dBFS) -2 -3 -4 -5 -6 0 1 2 3 4 5 6 7 8 INPUT FREQUENCY (MHz)
100
10 FULL POWER-DOWN PARTIAL POWER-DOWN 1
fSCLK = 32MHz AIN = -0.1dBFS
0.1 0.001
0.01
0.1 fCNVST (MHz)
1
10
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11
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
Pin Description
PIN 1 2 3 4 5 6 7 8 9 NAME AIN0P AIN0N AIN1P AIN1N REF SHDN BIP/UNI AGND CHSEL Positive Analog-Input Channel 0 Negative Analog-Input Channel 0 Positive Analog-Input Channel 1 Negative Analog-Input Channel 1 External Reference Voltage Input. VREF = 1V to (AVDD + 50mV). Bypass REF to AGND with a 0.1F and a 1F. Shutdown Input. Pull SHDN low to enter full power-down mode. Drive SHDN high to resume normal operation regardless of previous software entered into power-down mode. Analog-Input-Mode Select. Drive BIP/UNI high to select bipolar-input mode. Pull BIP/UNI low to select unipolar-input mode. Analog Ground. Connect all AGNDs and EP to the same potential. Channel-Select Input. Drive CHSEL high to select channel 1. Pull CHSEL low to select channel 0. Conversion-Start Input. The first rising edge of CNVST powers up the MAX1332/MAX1333 and begins acquiring the analog input. A falling edge samples the analog input and starts a conversion. CNVST also controls the power-down mode of the device (see the Partial Power-Down (PPD) and Full PowerDown (FPD) Mode section). Serial-Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed. Serial-Data Output. Data is clocked out on the rising edge of SCLK (see the Starting a Conversion section). Positive-Digital-Supply Input. DVDD is the positive supply input for the digital section of the MAX1332/MAX1333. Connect DVDD to a 2.7V to 3.6V power supply. Bypass DVDD to DGND with a 0.1F capacitor in parallel with a 1F capacitor. Place the bypass capacitors as close to the device as possible. Digital Ground. Ensure that the potential difference between AGND and DGND is less than 0.3V. Positive-Analog-Supply Input. AVDD is the positive supply input for the analog section of the MAX1332/MAX1333. Connect AVDD to a 4.75V to 5.25V power supply for the MAX1332. Connect AVDD to a 2.7V to 3.6V power supply for the MAX1333. Bypass AVDD to AGND with a 0.1F capacitor in parallel with a 1F capacitor. Place the bypass capacitors as close to the device as possible. Analog Ground. Connect all AGNDs and EP to the same potential. Exposed Paddle. Internally connected to AGND. Connect the exposed paddle to the analog ground plane. FUNCTION
10
CNVST
11 12
SCLK DOUT
13
DVDD
14
DGND
15
AVDD
16 --
AGND EP
12
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
Detailed Description
The MAX1332/MAX1333 use an input track and hold (T/H) circuit along with a successive-approximation register (SAR) to convert a differential analog input signal to a digital 12-bit output. The serial interface requires only three digital lines (SCLK, CNVST, and DOUT) and provides easy interfacing to microcontrollers (Cs) and DSPs. Figure 2 shows the simplified block diagram for the MAX1332/MAX1333.
AVDD DVDD CHSEL BIP/UNI AIN0P AIN0N AIN1P AIN1N REF MAX1332 MAX1333 CNVST SCLK SHDN INPUT MUX AND T/H 12-BIT SAR ADC OUTPUT BUFFER DOUT
MAX1332/MAX1333
Power Supplies
The MAX1332/MAX1333 accept two power supplies that allow the digital noise to be isolated from sensitive analog circuitry. For both the MAX1332 and MAX1333, the digital power-supply input accepts a supply voltage of +2.7V to +3.6V. However, the supply voltage range for the analog power supply is different for each device. The MAX1332 accepts a +4.75V to +5.25V analog power supply, and the MAX1333 accepts a +2.7V to +3.6V analog power supply. See the Layout, Grounding, and Bypassing section for information on how to isolate digital noise from the analog power input. The MAX1332/MAX1333s' analog power supply consists of one AVDD input, two AGND inputs, and the exposed paddle (EP). The digital power input consists of one DVDD input and one DGND input. Ensure that the potential on both AGND inputs is the same. Furthermore, ensure that the potential between AGND and DGND is limited to 0.3V. Ideally there should be no potential difference between AGND and DGND. There are no power sequencing issues between AVDD and DVDD. The analog and digital power supplies are insensitive to power-up sequencing.
CONTROL LOGIC AND TIMING
AGND
DGND
Figure 2. Simplified Functional Diagram
the acquisition time lengthens. The acquisition time, tACQ, is the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ k x (RSOURCE + RIN) x CIN where: k = 9 ln (2 x 2N ) The constant k is the number of RC time constants required so that the voltage on the internal sampling capacitor reaches N-bit accuracy, i.e., so that the difference between the input voltage and the sampling capacitor voltage is equal to 0.5 LSB. N = 12 for the MAX1332/MAX1333. RIN = 250 is the equivalent differential analog input resistance, CIN = 14pF is the equivalent differential analog input capacitance, and R SOURCE is the source impedance of the input signal. Note that tACQ is never less than 52s for the MAX1332 and 78s for the MAX1333, and any source impedance below 160 does not significantly affect the ADC's AC performance.
True-Differential Analog Input T/H
The equivalent input circuit of Figure 3 shows the MAX1332/MAX1333s' input architecture, which is composed of a T/H, a comparator, and a switched-capacitor DAC. On power-up, the MAX1332/MAX1333 enter full power-down mode. Drive CNVST high to exit full power-down mode and to start acquiring the input. The positive input capacitor is connected to AIN_P and the negative input capacitor is connected to AIN_N. The T/H enters its hold mode on the falling edge of CNVST and the ADC starts converting the sampled difference between the analog inputs. Once a conversion has been initiated, the T/H enters acquisition mode for the next conversion on the 13th falling edge of SCLK after CNVST has been transitioned from high to low. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. If the input signal's source impedance is high,
Input Bandwidth
The ADC's input-tracking circuitry has a 5MHz smallsignal bandwidth, making it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band
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13
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
AVDD CAPACITIVE DAC CIN+ AIN_P CONTROL LOGIC RIN+
COMP CINAIN_N RIN-
AGND
Figure 3a. Equivalent Input Circuit (Acquisition Mode)
AVDD
CAPACITIVE DAC CIN+ RIN+
AIN_P CONTROL LOGIC
COMP CINAIN_N RIN-
AGND
Figure 3b. Equivalent Input Circuit (Hold/Conversion Mode)
of interest, lowpass or bandpass filtering is recommended to limit the bandwidth of the input signal.
wideband amplifier that settles quickly and is stable with the ADC's 14pF input capacitance. See the Maxim website (www.maxim-ic.com) for application notes on how to choose the optimum buffer amplifier for an ADC application. The MAX4430 is one of the devices that is ideal for this application.
Input Buffer
To improve the input signal bandwidth under AC conditions, drive the input with a wideband buffer (>50MHz) that can drive the ADC's input capacitance (14pF) and settle quickly. Most applications require an input buffer to achieve 12-bit accuracy. Although slew rate and bandwidth are important, the most critical input buffer specification is settling time. The sampling requires an acquisition time of 52s for the MAX1332 and 78s for the MAX1333. At the beginning of the acquisition, the ADC internal sampling capacitors connect to the analog inputs, causing some disturbance. Ensure the amplifier is capable of settling to at least 12-bit accuracy during this interval. Use a low-noise, low-distortion,
14
Differential Analog Input Range and Protection
The MAX1332/MAX1333 produce a digital output that corresponds to the differential analog input voltage as long as the differential analog inputs are within the specified range. When operating in unipolar mode (BIP/UNI = 0), the usable differential analog input range is from 0 to V REF. When operating in bipolar mode (BIP/UNI = 1), the differential analog input range is from -V REF /2 to +V REF /2. In both unipolar and bipolar
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
CNVST
tSETUP
tHOLD
tCSW
SCLK
tCP tDOT
DOUT
tCFDE tDHOLD
tCRDD
Figure 4. Detailed Serial-Interface Timing
tCONV CNVST tSETUP SCLK 1 2 3 4 5 POWER- MODE SELECTION WINDOW 6 7 8 9 10 11 12 13 14 tACQ 15 16
CONTINUOUS-CONVERSION SELECTION WINDOW DOUT HIGH-Z 0 0 0 D11 D10 D9 HOLD D8 D7 D6 D5 D4 D3 D2 D1 D0 0
ANALOG INPUT TRACK AND HOLD STATE
TRACK
Figure 5. Interface Timing Sequence
modes, the input common-mode voltage can vary as long as the voltage at any single analog input (VAIN_P, VAIN_N) remains within 50mV of the analog power supply rails (AVDD, AGND). As shown in Figure 3, internal protection diodes confine the analog input voltage within the region of the analog power-supply rails (AVDD, AGND) and allow the analog input voltage to swing from AGND - 0.3V to AVDD + 0.3V without damage. Input voltages beyond AGND - 0.3V and AVDD + 0.3V forward bias the internal protection diodes. In this situation, limit the forward diode current to 50mA to avoid damaging the MAX1332/MAX1333.
and Full Power-Down (FPD) Mode section). SCLK clocks data out of the serial interface and sets the conversion speed. Figures 4 and 5 show timing diagrams that outline the serial-interface operation.
Starting a Conversion
On power-up, the MAX1332/MAX1333 enter full powerdown mode. The first rising edge of CNVST exits the full power-down mode and the MAX1332/MAX1333 begin acquiring the analog input. A CNVST falling edge initiates a conversion sequence. The T/H stage holds the input voltage; DOUT changes from high impedance to logic low; and the ADC begins to convert at the first SCLK rising edge. SCLK is used to drive the conversion process, and it shifts data out of DOUT. SCLK begins shifting out the data after the 4th rising edge of SCLK. DOUT transitions tDOT after each SCLK's rising edge and remains valid for tDHOLD after the next rising edge. The 4th rising clock edge produces the MSB of the conversion result at DOUT, and the MSB remains valid tDHOLD after the 5th rising edge of SCLK. Sixteen
15
Serial Digital Interface
Timing and Control
Conversion-start and data-read operations are controlled by the CNVST and SCLK digital inputs. CNVST controls the state of the T/H as well as when a conversion is initiated. CNVST also controls the power-down mode of the device (see the Partial Power-Down (PPD)
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
CNVST
SCLK
1
13
16
1
DOUT
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 6. Continuous Conversion with Burst or Continuous Clock
CNVST ONE 8-BIT TRANSFER SCLK 1ST SCLK RISING EDGE DOUT 0 0 0 D11 D10 D9 D8 D7
CONVST MUST GO HIGH AFTER 4TH BUT BEFORE 13TH SCLK RISING EDGE
DOUT GOES HIGH IMPEDANCE ONCE CONVST GOES HIGH
MODE
NORMAL
PPD
Figure 7. SPI Interface--Partial Power-Down
rising SCLK edges are needed to clock out the three leading zeros, 12 data bits, and a trailing zero. For continuous operation, pull CNVST high between the 14th and the 15th rising edges of SCLK. The highest throughput is achieved when performing continuous conversions. If CNVST is low during the rising edge of the 16th SCLK, the DOUT line goes to a high-impedance state on either CNVST's rising edge or the next SCLK's rising edge, enabling the serial interface to be shared by multiple devices. Figure 6 illustrates a conversion using a typical serial interface.
of the SCLK to enter partial power-down mode (see Figure 7). Drive CNVST low and then drive high before the 4th SCLK to remain in partial power-down mode. This reduces the supply current to 3.3mA. Drive CNVST low and allow at least 13 SCLK cycles to elapse before driving CNVST high to exit partial power-down mode. Full power-down mode reduces the supply current to 0.2A and is ideal for infrequent data sampling. To enter full power-down mode, the MAX1332/MAX1333 must first be in partial power-down mode. While in partial power-down mode, repeat the sequence used to enter partial power-down mode to enter full powerdown mode (see Figure 8). Drive CNVST low and allow at least 13 SCLK cycles to elapse before driving CNVST high to exit full power-down mode. Maintain a logic low or a logic high on SCLK and all digital inputs at DVDD or DGND while in either partial power-down or full power-down mode to minimize power consumption.
Partial Power-Down (PPD) and Full PowerDown (FPD) Mode
Power consumption is reduced significantly by placing the MAX1332/MAX1333 in either partial power-down mode or full power-down mode. Partial power-down mode is ideal for infrequent data sampling and fast wake-up time applications. Once CNVST is transitioned from high to low, pull CNVST high any time after the 4th rising edge of the SCLK but before the 13th rising edge
16
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
CNVST 1ST 8-BIT TRANSFER SCLK 1ST SCLK RISING EDGE DOUT 0 0 0 D11 D10 D9 1ST SCLK RISING EDGE D8 D7 0 0 0 0 0 0 0 0 EXECUTE PARTIAL POWER-DOWN TWICE 2ND 8-BIT TRANSFER
MODE
NORMAL
PPD
RECOVERY
FPD
Figure 8. SPI Interface--Full Power-Down
FFF FFE FFD OUTPUT CODE (hex) FFC FFB
FS = VREF ZS = 0 1 LSB = VREF 4096
FULL-SCALE TRANSITION
7FF 7FE
+FS = VREF 2 ZS = 0 -VREF 2 V 1 LSB = REF 4096 -FS =
FULL-SCALE TRANSITION
OUTPUT CODE (hex) 0 1 2 3 4 FS
001 000 FFF FFE
004 003 002 001 000 FS - 1.5 LSB DIFFERENTIAL INPUT VOLTAGE (LSB)
801 800 -FS 0 -FS + 0.5 LSB +FS - 1.5 LSB DIFFERENTIAL INPUT VOLTAGE (LSB) +FS
Figure 9. Unipolar Transfer Function
Figure 10. Bipolar Transfer Function
Another way of entering the full power-down mode is using the SHDN input. Drive SHDN to a logic low to put the device into the full power-down mode. Drive SHDN high to exit full power-down mode and return to normal operating mode. SHDN overrides any software-controlled power-down mode and every time it is deasserted, it places the MAX1332/MAX1333 in its normal mode of operation regardless of its previous state.
Transfer Function
The MAX1332/MAX1333 output is straight binary in unipolar mode and is two's complement in bipolar mode. Figure 9 shows the unipolar transfer function for the MAX1332/MAX1333. Table 1 shows the unipolar relationship between the differential analog input voltage and the digital output code. Figure 10 shows the bipolar transfer function for the MAX1332/MAX1333. Table 2 shows the bipolar relationship between the differential analog input voltage and the digital output code.
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
Table 1. Unipolar Code Table (MAX1332)
BINARY DIGITAL OUTPUT CODE D11-D0 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 HEXADECIMAL EQUIVALENT OF D11-D0 0xFFF 0xFFE 0x801 0x800 0x7FF 0x001 0x000 DECIMAL EQUIVALENT OF D11-D0 (CODE10) 4095 4094 2049 2048 2047 1 0 DIFFERENTIAL INPUT VOLTAGE (V) (VREF = 4.096V ) +4.095 0.5 LSB +4.094 0.5 LSB +2.049 0.5 LSB +2.048 0.5 LSB +2.047 0.5 LSB +0.001 0.5 LSB +0.000 0.5 LSB
Table 2. Bipolar Code Table (MAX1332)
TWO's-COMPLEMENT DIGITAL OUTPUT CODE D11-D0 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0001 1000 0000 0000 HEXADECIMAL EQUIVALENT OF D11-D0 0x7FF 0x7FE 0x001 0x000 0xFFF 0x801 0x800 DECIMAL EQUIVALENT OF D11-D0 (CODE10) +2047 +2046 +1 0 -1 -2047 -2048 DIFFERENTIAL INPUT VOLTAGE (V) (VREF = 4.096V) +2.047 0.5 LSB +2.046 0.5 LSB +0.001 0.5 LSB 0.000 0.5 LSB -0.001 0.5 LSB -2.047 0.5 LSB -2.048 0.5 LSB
Determine the differential analog input voltage as a function of VREF and the digital output code with the following equation: VAIN = LSB x CODE10 0.5 x LSB where: VAIN = VAIN _ P - VAIN _ N V V LSB = REF = REF 212 4096 CODE10 = the decimal equivalent of the digital output code (see Tables 1 and 2). 0.5 x LSB represents the quantization error that is inherent to any ADC. When using a 4.096V reference, 1 LSB equals 1.0mV. When using a 2.5V reference, 1 LSB equals 0.61mV.
Applications Information
External Reference
The MAX1332/MAX1333 use an external reference between 1V and (AV DD + 50mV). Bypass REF with a 1F capacitor in parallel with a 0.1F capacitor to AGND for best performance (see the Typical Operating Circuit).
Connection to Standard Interfaces
The MAX1332/MAX1333 serial interface is fully compatible with SPI, QSPI and MICROWIRE (see Figure 11). If a serial interface is available, set the C's serial interface in master mode so the C generates the serial clock. Choose a clock frequency based on the AVDD and DVDD amplitudes.
SPI and MICROWIRE
When using SPI or MICROWIRE, the MAX1332/ MAX1333 are compatible with all four modes programmed with the CPHA and CPOL bits in the SPI or MICROWIRE control register. (This control register is in
18
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
the bus master, not the MAX1332/MAX1333.) Conversion begins with a CNVST falling edge. DOUT goes low, indicating a conversion is in progress. Two consecutive 1-byte reads are required to get the full 12 bits from the ADC. DOUT transitions on SCLK rising edges and is guaranteed to be valid tDOT later and remain valid until tDHOLD after the following SCLK rising edge. When using CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1, the data is clocked into the C on the following or next SCLK rising edge. When using CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA = 0, the data is clocked into the C on the next falling edge. See Figure 11 for connections and Figures 12 and 13 for timing. See the Timing Characteristics table to determine the best mode to use.
MAX1332/MAX1333
I/O SCK MISO +3V TO +5V
CNVST SCLK DOUT
SS a) SPI CS SCK MISO +3V TO +5V
MAX1332 MAX1333
CNVST SCLK DOUT
QSPI
Unlike SPI, which requires two 1-byte reads to acquire the 12 bits of data from the ADC, QSPI allows acquiring the conversion data with a single 16-bit transfer. The MAX1332/MAX1333 require 16 clock cycles from the C to clock out the 12 bits of data. Figure 14 shows a transfer using CPOL = 1 and CPHA = 1. The conversion result contains three zeros, followed by the 12 data bits and a trailing zero with the data in MSB-first format.
b) QSPI
SS
MAX1332 MAX1333
I/O SK SI
CNVST SCLK DOUT
MAX1332 MAX1333
c) MICROWIRE
DSP Interface to the TMS320C54_
The MAX1332/MAX1333 can be directly connected to the TMS320C54_ family of DSPs from Texas Instruments. Set the DSP to generate its own clocks or use external clock signals. Use either the standard or buffered serial port. Figure 15 shows the simplest interface between the MAX1332/MAX1333 and the TMS320C54_, where the transmit serial clock (CLKX) drives the receive serial clock (CLKR) and SCLK, and the transmit frame sync (FSX) drives the receive frame sync (FSR) and CNVST. For continuous conversion, set the serial port to transmit a clock and pulse the frame sync signal for a clock period before data transmission. Use the serial port configuration (SPC) register to set up with internal frame sync (TXM = 1), CLKX driven by an on-chip clock source (MCM = 1), burst mode (FSM = 1), and 16-bit word length (FO = 0). This setup allows continuous conversions provided that the data transmit register (DXR) and the data-receive register (DRR) are serviced before the next conversion. Alternately, autobuffering can be enabled when using the buffered serial port to execute conversions and read the data without C intervention. Connect DVDD to the TMS320C54_ supply voltage. The word length can be set to 8 bits with FO = 1 to implement the power-
Figure 11. Common Serial-Interface Connections to the MAX1332/MAX1333
down modes. The CNVST pin must idle high to remain in either power-down state. Another method of connecting the MAX1332/MAX1333 to the TMS320C54_ is to generate the clock signals external to either device. This connection is shown in Figure 16 where serial clock (CLOCK) drives the receive serial clock (CLKR) and SCLK, and the convert signal (CONVERT) drives the receive frame sync (FSR) and CNVST. The serial port must be set up to accept an external receive clock and external receive frame sync. Write the serial port configuration (SPC) register as follows: * TXM = 0, external frame sync * MCM = 0, CLKX is taken from the CLKX pin * FSM = 1, burst mode * FO = 0, data transmitted/received as 16-bit words This setup allows continuous conversion provided that the data-receive register (DRR) is serviced before the next conversion. Alternately, autobuffering can be
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19
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
CNVST
SCLK
1
8
9
16
DOUT
HIGH IMPEDANCE
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
1ST BYTE READ
2ND BYTE READ
Figure 12. SPI/MICROWIRE Serial-Interface Timing--Single Conversion
CNVST
SCLK
1
13
14
16
1
DOUT
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing--Continuous Conversion
CNVST
SCLK
1
2
16
DOUT
HIGH IMPEDANCE
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
Figure 14. QSPI Serial-Interface Timing
DVDD SCLK
DVDD CLKX CLKR FSX FSR TMS320C54x
DVDD SCLK
DVDD CLKR TMS320C54x FSR DR CLOCK CONVERT
MAX1332 MAX1333 CNVST
MAX1332 CNVST MAX1333 DOUT
DOUT
DR
Figure 15. Interfacing to the TMS320C54_ Internal Clocks 20
Figure 16. Interfacing to the TMS320C54_ External Clocks
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
CNVST
SCLK
1
8
16
1
DOUT
D0
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 17. DSP Interface--Continuous Conversion
CNVST
SCLK
1
1
DOUT
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Figure 18. DSP Interface--Single Conversion--Continuous/Burst Clock
enabled when using the buffered serial port to read the data without C intervention. Connect DV DD to the TMS320C54_ supply voltage. The MAX1332/MAX1333 can also be connected to the TMS320C54_ by using the data transmit (DX) pin to drive CNVST and the transmit clock (CLKX) generated internally to drive SCLK. A pullup resistor is required on the CNVST signal to keep it high when DX goes high impedance and write (0001)h to the data transmit register (DXR) continuously for continuous conversions. The power-down modes can be entered by writing (00FF)h to the DXR (see Figures 17 and 18).
high frame (LTFS = 0, LRFS = 0) signal. In this mode, the data-independent frame-sync bit (DITFS = 1) can be selected to eliminate the need for writing to the transmit data register more than once. For single conversions, idle CNVST high and pulse it low for the entire conversion. Configure the ADSP21_ _ _ STCTL and SRCTL registers for late framing (LAFR = 1) and for an active-low frame (LTFS = 1, LRFS = 1) signal. This is also the best way to enter the power-down modes by setting the word length to 8 bits (SLEN = 0111). Connect the DVDD pin to the ADSP21_ _ _ supply voltage (see Figures 17 and 18).
DSP Interface to the ADSP21_ _ _
The MAX1332/MAX1333 can be directly connected to the ADSP21_ _ _ family of DSPs from Analog Devices. Figure 19 shows the direct connection of the MAX1332/MAX1333 to the ADSP21_ _ _. There are two modes of operation that can be programmed to interface with the MAX1332/MAX1333. For continuous conversions, idle CNVST low and pulse it high for one clock cycle during the LSB of the previous transmitted word. Configure the ADSP21_ _ _ STCTL and SRCTL registers for early framing (LAFR = 0) and for an active-
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap boards must not be used. Board layout must ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 20 shows the recommended system ground connections. Establish an analog ground point at AGND and a digital ground point at DGND. Connect all other analog grounds to the analog ground point.
21
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
ANALOG SUPPLY AVDD DVDD SCLK VDDINT TCLK RCLK TFS RFS DOUT DR AVDD AGND DGND DVDD DATA DGND DVDD ADSP21_ _ _ 10* RETURN DIGITAL GROUND POINT DIGITAL SUPPLY RETURN DVDD
ANALOG GROUND POINT
MAX1332 MAX1333 CNVST
MAX1332 MAX1333
*OPTIONAL
DIGITAL CIRCUITRY
Figure 19. Interfacing to the ADSP21_ _ _
Figure 20. Power-Supply Grounding Condition
Connect all digital grounds to the digital ground point. For lowest noise operation, make the power supply returns as low impedance and as short as possible. Connect the analog ground point to the digital ground point together at the IC. High-frequency noise in the power supplies degrades the ADC's performance. Bypass AVDD to AGND with 0.1F and 1F bypass capacitors. Likewise, bypass DVDD to DGND with 0.1F and 1F bypass capacitors. Minimize capacitor lead lengths for best supply noise rejection. To reduce the effects of supply noise, a 10 resistor can be connected as a lowpass filter to attenuate supply noise (see Figure 20).
the transfer function once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics table.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1332/ MAX1333, DNL deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics table.
Exposed Paddle
The MAX1332/MAX1333 TQFN package has an exposed paddle on the bottom of the package, providing a very low thermal resistance path for heat removal from the IC, as well as a low-inductance path to ground. The pad is electrically connected to AGND on the MAX1332/ MAX1333 and must be soldered to the circuit board analog ground plane for proper thermal and electrical performance. Refer to the Maxim Application Note HFAN-08.1: Thermal Considerations for QFN and Other Exposed Pad Packages, for additional information.
Offset Error
Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero-scale of the transfer function or at or near the midscale of the transfer function. For the MAX1332/MAX1333, operating with a unipolar transfer function, the ideal zero-scale digital output transition from 0x000 to 0x001 occurs at 0.5 LSB above AGND. Unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point. For the MAX1332/MAX1333, operating with a bipolar transfer function, the ideal midscale digital output transition from 0xFFF to 0x000 occurs at 0.5 LSB below AGND. Bipolar offset error is the amount of deviation
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer function from a straight line. For the MAX1332/ MAX1333, this straight line is between the end points of
22
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
CNVST
tion error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. For the MAX1332/MAX1333, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
TRACK
MAX1332/MAX1333
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
T/H
TRACK
HOLD
Signal-to-Noise Plus Distortion (SINAD)
SINAD is a dynamic figure of merit that indicates the converter's noise and distortion performance. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset: SIGNALRMS SINAD(dB) = 20 x log (NOISE + DISTORTION)RMS
Figure 21. T/H Aperture Timing
between the measured midscale transition point and the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1332/ MAX1333, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. For the unipolar input, the full-scale transition point is from 0xFFE to 0xFFF and the zero-scale transition point if from 0x000 to 0x001. For the bipolar input, the full-scale transition point is from 0x7FE to 0x7FF and the zero-scale transition point is from 0x800 to 0x801.
Effective Number of Bits (ENOB)
ENOB specifies the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a fullscale sinusoidal input waveform is computed from: ENOB = SINAD -1.76 6.02
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay.
Total Harmonic Distortion (THD)
THD is a dynamic figure of merit that indicates how much harmonic distortion the converter adds to the signal. THD is the ratio of the RMS sum of the first five harmonics of the fundamental signal to the fundamental itself. This is expressed as: V22 + V32 + V42 + V52 + V62 THD = 20 x log V1
Aperture Delay
Aperture delay (tAD) is the time defined between the falling edge of the CNVST and the instant when an actual sample is taken (Figure 21).
Signal-to-Noise Ratio (SNR)
SNR is a dynamic figure of merit that indicates the converter's noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantiza-
where V1 is the fundamental amplitude, and V2 through V6 are the amplitudes of the 2nd- through 6th-order harmonics.
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3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs MAX1332/MAX1333
Spurious-Free Dynamic Range (SFDR)
SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB.
Power-Supply Rejection (PSR)
PSR is defined as the shift in offset error when the analog power supply is moved from 2.7V to 3.6V.
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones fIN1 and fIN2. The individual input tone levels are at -7dBFS. The intermodulation products are as follows: * 2nd-order intermodulation products (IM2): f IN1 + fIN2, fIN2 - fIN1 * 3rd-order intermodulation products (IM3): 2fIN1 fIN2, 2fIN2 - fIN1, 2fIN1 + fIN2, 2fIN2 + fIN1 * 4th-order intermodulation products (IM4): 3f IN1 fIN2, 3fIN2 - fIN1, 3fIN1 + fIN2, 3fIN2 + fIN1 * 5th-order intermodulation products (IM5): 3f IN1 2fIN2, 3fIN2 - 2fIN1, 3fIN1 + 2fIN2, 3fIN2 + 2fIN1
DOUT SCLK
Pin Configuration
CNVST 10 CHSEL 9
TOP VIEW
12 DVDD 13 DGND 14 AVDD 15 AGND 16
11
8 7
AGND BIP/UNI SHDN REF
MAX1332 MAX1333
6 5
1
2
3 AIN1P
AIN0N
Channel-to-Channel Isolation
Channel-to-channel isolation is a figure of merit that indicates how well each analog input is isolated from the others. The channel-to-channel isolation for the MAX1332/MAX1333 is measured by applying a low-frequency 500kHz -0.5dBFS sine wave to the on channel while a high-frequency 900kHz -0.5dBFS sine wave is applied to the off channel. An FFT is taken for the on channel. From the FFT data, channel-to-channel crosstalk is expressed in dB as the power ratio of the 500kHz low-frequency signal applied to the on channel and the 900kHz high-frequency crosstalk signal from the off channel.
Selector Guide
PART MAX1332ETE MAX1333ETE AVDD (V) +5 +3 MAX SAMPLING RATE (Msps) 3 2
Full-Power Bandwidth
A large -0.5dB FS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. PROCESS: BiCMOS
Chip Information
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the signal-to-noise plus distortion (SINAD) is equal to 68dB. The amplitude of the analog input signal is -0.5dBFS.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an ADC in such a way that the signal's slew rate does not limit the ADC's performance. The input frequency is
24 ______________________________________________________________________________________
AIN1N
AIN0P
4
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
MAX1332/MAX1333
D2 b
0.10 M C A B
D D/2
D2/2
E/2
E2/2
C L
E
(NE - 1) X e
E2
L
C L
e
k (ND - 1) X e
C L
0.10 C 0.08 C A A2 A1 L
C L
L
e
e
PACKAGE OUTLINE 12, 16L, THIN QFN, 3x3x0.8mm
21-0136
E
1
2
PKG REF. A b D E e L N ND NE A1 A2 k 0.25 0 MIN. 0.70 0.20 2.90 2.90 0.45
12L 3x3 NOM. 0.75 0.25 3.00 3.00 0.50 BSC. 0.55 12 3 3 0.02 0.20 REF 0.05 0 0.25 0.65 0.30 MAX. 0.80 0.30 3.10 3.10 MIN. 0.70 0.20 2.90 2.90
16L 3x3 NOM. 0.75 0.25 3.00 3.00 0.50 BSC. 0.40 16 4 4 0.02 0.20 REF 0.05 0.50 MAX. 0.80 0.30 3.10 3.10 PKG. CODES T1233-1 T1233-3 T1633-1 T1633-2 T1633F-3 T1633-4
EXPOSED PAD VARIATIONS
D2 MIN. 0.95 0.95 0.95 0.95 0.65 0.95 NOM. 1.10 1.10 1.10 1.10 0.80 1.10 MAX. 1.25 1.25 1.25 1.25 0.95 1.25 MIN. 0.95 0.95 0.95 0.95 0.65 0.95 E2 NOM. MAX. 1.10 1.10 1.10 1.10 0.80 1.10 1.25 1.25 1.25 1.25 0.95 1.25 PIN ID 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 JEDEC WEED-1 WEED-1 WEED-2 WEED-2
DOWN BONDS ALLOWED
NO YES NO YES N/A NO
0.225 x 45 WEED-2 0.35 x 45 WEED-2
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PACKAGE OUTLINE 12, 16L, THIN QFN, 3x3x0.8mm
21-0136
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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